Publications

RESEARCH PUBLICATIONS

S.No.	Name Of Faculty	Papers in Research Journals		Paper in Conferences		Total
S.No.	Name Of Faculty	Int. J.	Nat. J.	Int. C.	Nat. C.	Total
1.	Dr. (Mrs.) Rajeevan Chandel	15	9	36	41	101
2.	Dr. Lalit Awasthi					89
3.	Dr. (Mrs.) Kamlesh Dutta					80
4.	Er. Gargi Khanna	3	-	12	23	38
5.	Dr. Ashwani K. Rana	27	01	21	30	79
6.	Er. Gagnesh Kumar	01	01	02	04	8
7.	Er. Philemon Daniel	1	1	1	5	8
8.	Er. Himanshu Sharma	-	1	-	1	2
9.	Er. Rohit Dhiman	01	-	06	01	8
10.	Er. Shweta Chauhan	-	-	-	-
TOTAL PUBLICATIONS						369

The Faculty of the Department of E&CE has contributed over 250 research publications

Papers Presented in National / International Conferences in which SMDP-II Financial Support has been used

Financial Year	Detail of Publication (DIT duly acknowledged in the Paper )	Name of Faculty/ Students to whom Support is provided under SMDP
2008-09	Manabesh, Pradeep, Uttpal, Rajeevan Chandel, Face Recognition by Gabor Wavelet, International Conference on Cognition & Recognition ICCR08, PES College of Engineering, Mandiya, Karnataka, pp.161-167, 10-12 April 2008.	Manabesh Ray Pradeep Kr. Subudhi
2008-09	Gargi Khanna, Preeti, Rajeevan Chandel, S. Sarkar, Cross-talk Mitigation in Coupled VLSI Interconnects, International IEEE VLSI Design & Test Symposium (VDAT-2008), Bangalore, pp.364-374, 23-26 July 2008.	Dr. R. Chandel Er. Gargi Khanna
2009-10	Samarth, Ashok, Gargi, International Conference at TU Patiala	Samarth
2010-11	VDAT-2010	Er. Sunil Jadav
2010-11	VDAT-2010	Er. P Daniel
2010-11	VDAT-2010	Dr. Rajeevan Chandel & Er. Gargi Khanna
2011-12	International Conference Wireless Vitae-2011	Dhrub Solanki
	International Conference IISN-11	Purnima Sharma
	International Conference at BITS Mesra	Deepesh Ranka
	International Conference at Jodhpur	Diwakar Singh
	National Workshop RAMEMS-11	Atul K. Nishad

PUBLICATIONS IN NATIONAL/INTERNATIONAL JOURNALS (year wise)

Sr. No.	Title	Author	Name of Journal	Publisher	Vol. & Issue, Page	Year
1.	Investigations on Interchannel Cross- talk at ADM for an Optical Ring Network	Vinod Kumar, Ajay K. Sharma, R.A. Agarwala	OPTIK - International Journal for Lightand Electron Optics	Elsevier Science, Germany	Vol. Optik 121 PP 45-49	2010
2.	Analytical Investigations on Cross-talk in Fiber Raman Amplification for WDM Systems	Vinod Kumar, Ajay K. Sharma, R. A. Agarwala	OPTIK - International Journal for Light and Electron Optics	Elsevier Science, Germany	Vol. Optik 121 PP 50-53	2011
3.	Performance evaluation of SCM- WDM communication in the presence of SRS induced crosstalk for different types of ﬁber	Naresh Kumar, Ajay K. Sharma, Vinod Kapoor	International Journal for Light and Electron Optics OPTIK	Elsevier	Accepted & in Press-Dec.	2010
4.	Low Power CMOS VCO for Wide Band Communication Applications	Dhrub Solanki and Rajeevan Chandel	Electrical India	Chary Publications Pvt. Ltd.	Vol. 51, No. 2, pp. 46-52 Feb	2011
5.	Design and Analysis of LC -VCO using MEMS Spiral Inductor	Dhrub Solanki, RajeevanChandel, T.Alam, A. Nishad	International Journal of Micro and Nano Systems	Int. Sc. Press India	Vol. 2, No. 1, pp. 47-51	2011
6.	Design and Analysis of a Modified Low Power CMOS Full Adder Using Gate Diffusion Input Technique	Kiran K. Chaddha, Rajeevan Chandel	Journal of Low Power Electronics	ASP	Vol. 6, No. 4, pp. 482-490	2010
7.	Design and Analysis of Sub -DT Sub-Domino Logic Circuits for Ultra Low Power Applications	Ashutosh Nandi, Rajeevan Chandel	Journal of Low Power Electronics	ASP	Vol. 6, No. 4, pp. 513-520	2010
8.	A Comparative Analysis of Voltage- Scaled Two Operand Binary Adders	Rajeevan Chandel, Devesh P. Singh, R. Banta, R. Karan, P. Bhatt	Journal of Active and Passive Electronic Devices (JAPED)	Old city publishers	Vol.5, No.3-4, pp. 295-309	2010
9.	Genetic Algorithm Based Approach To Circuit Partitioning	Sandeep Singh Gill, RajeevanChandel, Ashwani Chandel	International Journal of Computer and Electrical Engineering (IJCEE)	International Association of Computer Science and Information Technology Press (IACSIT)	Vol. 2 No. 2, pp. 212-218	April 2010
10.	Comparative study of Ant Colony and Genetic Algorithms for VLSI circuit partitioning	Sandeep Singh Gill, RajeevanChandel, Ashwani Chandel	International Journal of Computer Systems Science and Engineering (IJCEE)	International Association of Computer Science and Information Technology Press (IACSIT)	Vol. 4, No. 2, pp. 104-108	2009
11.	Performance Analysis of Voltage-Scaled Static and Dynamic CMOS Circuits	Rajeevan Chandel, Y. Nataraj, Gargi khanna	Journal of Nanoelectronics & Optoelectronics (JNO)	ASP, USA	vol.3, no.2, pp. 171-176	2008
12.	Delay and Power Management of Voltage- Scaled Repeaters for Long Interconnects	Rajeevan Chandel, S. Sarkar and R.P. Agarwal	International Journal of Modelling & Simulation	ACTA Press, Canada	vol. 27, no. 4, pp. 333-339	2007
13.	Investigations on Short- Circuit Power Dissipation in Repeater Loaded VLSI Interconnects	Rajeevan Chandel, S. Sarkar, and Ashwani Chandel	Journal of Low Power Electronics	MDPI	vol. 3, no. 3, pp. 337-344	2007
14.	An Analysis of Interconnect Delay Minimization by Low- Voltage Repeater Insertion	Rajeevan Chandel, S. Sarkar and R.P. Agarwal	Micro electronics Journal	Elsevier Science	Vol. 38, No. 4-5, pp. 649-655	April-May 2007
15.	Repeater stage timing analysis for VLSI resistive interconnects	Rajeevan Chandel, S. Sarkar and R.P. Agarwal	Micro electronics International	Emerald UK	Vol. 23, No. 3, pp. 19-25	2006
16.	Repeater insertion in global interconnects in VLSI circuits	Rajeevan Chandel, S. Sarkar and R.P. Agarwal	Micro electronics International	Emerald UK	Vol. 22, No. 1, pp. 43-50	Jan 2005
17.	Delay Analysis of a Single Voltage- Scaled- Repeater driven Long Interconnect	Rajeevan Chandel, S. Sarkar and R.P. Agarwal	Micro electronics International	Emerald UK	Vol. 22, No. 3, pp. 28-33	2005
18.	Transition Time Considerations in Voltage- Scaled Repeaters	Rajeevan Chandel, S. Sarkar and R.P. Agarwal	Micro electronics International	Emerald UK	Vol. 22, No. 3, pp. 39-40	2005
19.	High Speed Energy Efficient signal Transmission on Global VLSI Interconnect	Sunil Jadav, Gargi Khanna and Ashok Kumar	International Journal of Information and Tele communication Technology		pp. 52 -56	Nov. 06, 2010.
20.	A new fuzzy based localization error minimization approach with optimized beacon range	Vinay Kumar, Ashok Kumar, Surender Soni	International Journal of Computer Application
21.	A Study of Physical Properties of Ge-Se-In Glassy Semiconductors	R. Kumar, A. Kumar, V.S. Rangra	Journal of Optoelectronic and Advanced Materials- Rapid Comm.		vol. 4, pp. 1554 -1558	2010
22.	Analysis of non-ideal effects in coupled VLSI interconnects with active and passive load variation	Gargi Khanna, Rajeevan Chandel, Ashwani Chandel, S.Sarkar	Micro electronics International	Emerald UK	vol. 26, no. 1 pp. 3-9	Jan. 2009.
23.	Analysis of non-ideal effects in coupled VLSI interconnects with active and passive load variation	Gargi Khanna, Rajeevan Chandel, Ashwani K. Chandel, S. Sarkar	Micro electronics International	Emerald UK	vol. 26, no. 1, pp. 3-9	2009.
24.	Analytic Modeling of Non- Uniform Graded Dopant Profile of Polysilicon Gate in Gate Tunneling Current for N- MOSFET in Nanoscale Regime	Ashwani Kumar, S.Dasgupta	Journal of Computational and Theoretical Nanoscience (CTN)	American scientific publisher	Vol 4, No 1, pp 179-185	2007
25.	Unified Compact Modeling of a gate Tunneling Current considering Image Force Induced Barrier Lowering for a nanoscale N-MOSFET	Ashwani Kumar, S.Dasgupta	Journal of Computational and Theoretical Nanoscience (CTN)	American scientific publisher	Vol 4, No 3, pp 482-487	2007
26.	Significance of Nanotechnology in construction Engineering	Ashwani K. Rana, Shashi B. Rana, Anjna Kumari, Vaishnav Kiran	International Journal of Recent trends in Engineering	Academy Publisher	Vol. 1, No. 4, pp 46-48	2009
27.	A Compact gate tunnel current model for nano scale MOSFET with sub+1nm gate oxide	Ashwani Kumar, Narottam Chand and Vinod Kapoor,	International Journal of Applied Engineering Research (IJAER)		Vol.1, No.1, PP 175-193	2010
28.	Trap assisted tunneling Model for gate current in nano scale MOSFET with high-K Gate dielectrics	Ashwani Kumar, Narottam Chand, Vinod Kapoor	International Journal of Electrical and Electronics Engineering-WASET Journal	WASET	Vol.3, No.7, PP 402-409	2009
29.	Analytical gate current modeling in nanoscale MOSFET with high gate static structure.	Ashwani Kumar, Narottam Chand, Vinod Kapoor	Journal of Electrical and Electronics Engineering.		Vol.3, No.2, PP 169-174	2010
30.	Impact of Gate Engineering on gate leakage behaviour of nanoscale MOSFET with high dielectrics	Ashwani Kumar, Narottam Chand, Vinod Kapoor	Journal of Nano Electronics and Opto electronics			Accepted and in press- Jan.2011
31.	Gate tunnel current calculation for NMOSFET based on Deep Sub-Micron Effects	Ashwani Kumar, Narottam Chand and Vinod Kapoor	International Journal of Electrical and Electronics Engineering	IEEE	Vol.3, No.1, PP 426-434	2009
32.	Comparative analysis and optimization of current mirrors	Vinod Kumar, Himanshu Sharma, Rituraj singh Rathore	Journal of Multi disciplinary Engineering Technologies	Bharti vidyapeeth College of Engineering, New Delhi	Vol 4 No.1, pp 29-33	July -Dec 2009
33.	A Flexible Programmable Memory BIST Architecture	Philemon Daniel, Rajeevan Chandel	IETE Journal of Education	IETE	Volume: 51, N0. 2, pp 67-74	2010
34.	Performance evaluation of Adaptive modulation of data spread OFDM	Rakesh Sharma, Sachin Dhaiya	IJEE	Serial Publications	Vol 1, Issue1, pp 27-30
35.	Delay Analysis of a CMOS Buffer Driven RLC Interconnect Load for Sub- Threshold Applications	Rohit Dhiman, Rajeevan Chandel	International Journal of Modelling and Simulation, ACTA Press	ACTA Press

TEXT BOOKS / MONOGRAPHS PUBLISHED

Sr. No.	Title	Faculty Name	Publisher	Vol. & Issue	Year
1.	Design Techniques for VLSI and communication-A Report	Rajeevan Chandel, Ashwani Kumar Chandel	http://vlsi-india.org/vsi/activities /events.html	N.A	August, 2007
2.	Study of Voltage-scaled Repeaters for Long Interconnects in VLSI Circuits	Rajeevan Chandel	IIT Roorkee	Ph.D. Thesis	July, 2005
3.	Electrostatic Microactuators Using Direct Wafer Bonding Technology	Rajeevan Chandel	IIT Delhi	M.Tech. Dissertation	December, 1997

Ph.D. GUIDANCE

S. No.	Title of the Ph.D. Thesis	Supervisor	Academic year	Name and Roll no. of the student(s)
1.	Optimal Design and Mitigation of Non- Ideal Effects in VLSI Interconnects	Dr. (Mrs.) Rajeevan Chandel Dr. Ashwani Kumar Chandel Asso. Prof. EED	2006	Er. Gargi Khanna, AP E&CE Department
2.	VLSI Circuit Partitioning using Evolutionary Optimization Techniques	Dr. (Mrs.) Rajeevan Chandel Dr. Ashwani Kumar Chandel	2007	Er. Sandeep Singh Gill, Asso. Prof. GNDEC, Ludhiana
3.	Gate Tunneling Current Models for Circuit Simulation of MOSFET Based Nanoscale Devices	Dr. Vinod Kapoor & Dr. Narottam Chand	2007	Mr. Ashwani K. Rana, AP E&CED
4.	Software Based Self-test Techniques for Online Test and Diagnosis of Embedded Circuits	Dr. (Mrs.) Rajeevan Chandel	2008	Er. Philemon Daniel, AP E&CED
5.	VLSI Interconnect Design for Ultra Low Power Regime	Dr. (Mrs.) Rajeevan Chandel	2009	Er. Rohit Dhiman, VLSI Faculty under SMDP-II